1. Field of the Invention
The present disclosure is related to thin film wafer level package and a method for forming such thin film wafer level package.
2. Description of the Related Art
With the increasing success of Micro Electro Mechanical Systems (MEMS) devices in the last decade comes a need for packaging technologies to encapsulate the MEMS device in a package. These packages serve to protect the often fragile MEMS device from, e.g., the processing environment during dicing and assembly of the substrate on which the MEMS device is formed. Furthermore these packages assist in providing an improved operation of the MEMS device and a sufficient lifetime thereof.
Several options exist to process the package on top of the MEMS device. There are the wafer-to-wafer approach, the chip-to-wafer approach and the use of a thin film encapsulation process. The first two approaches are expensive as they require processing of two different substrates while resulting in a packaged MEMS device having a large area and volume. The use of a thin film encapsulation process, often referred to as zero-level (0-level) packaging, to form a package over the MEMS device is more elegant, as it is a batch process. Moreover this approach results in a compact solution. Using poly-SiGe both as a structural material for the MEMS device and as the thin film packaging layer further enables the integration of a packaged MEMS device on a CMOS substrate thanks to the low deposition temperature of the poly-SiGe (<450° C.)
To ensure a robust 0-level package, which survives subsequent processing such as dicing, wirebonding, and the 1-level plastic molding packaging process, the shear strength of the package becomes very important.